Four compute roles
Scope and architectural emphasis without winner claims.
GPU vs NPU vs TPU vs CPU
Route the workload, then benchmark.
Trace a workload through device availability, software support, memory, and power constraints. See why a chip label cannot choose a system.
Live result
Four paths through your constraints
An editorial constraint tree, not a benchmark or compatibility certificate. “NPU” means a client inference NPU; “TPU” means Google Cloud TPU here. Those labels are not mutually exclusive architectural categories. CPU host work remains even when tensor work is offloaded.
The explanation
The system is a chain, not a chip.
CPU cores handle general program control; GPU execution exposes many parallel threads. Neither label alone reveals whether your particular operator, memory footprint, or latency target is well served. [C1]
The CPU prepares and schedules work, data must be accessible to the accelerator, and results must return to the application. Repeated transfers, synchronization, or memory pressure can dominate a fast kernel. Shared-memory systems change the path but do not remove the need to reason about locality. [C2]
A client NPU can be an energy-efficiency candidate for a supported inference graph. Unsupported operators, shapes, or formats may require conversion or fallback. This router asks you to enter support explicitly; it cannot infer compatibility from a file or device name. [C3]
Cloud TPUs organize substantial computation around matrix operations with associated vector and scalar processing. They remain a cloud path in this teaching model. Real procurement requires the exact generation, compiler, topology, measured workload, and full service cost. [C4]
headroomGiB = entered usable memory − entered working set
Open Asset Factory
Take the explanation with you.
Three independent diagrams. Editable source and high-resolution PNGs, with assumptions printed on the image.
Sources checked 2026-09-07
Claims you can inspect.
Formula derivations and teaching assumptions are documented separately.
Download claim ledgerNVIDIA describes CPU latency-oriented control and GPU parallel throughput as different design priorities.
Primary source ↗Qualitative architecture distinction; no universal speed ratio.
CUDA’s heterogeneous model uses CPU host code to launch GPU work and coordinate data, with memory arrangements varying by system.
Primary source ↗Integrated and discrete memory systems differ.
Microsoft documents execution providers, model-format requirements, and fallback when preferred hardware cannot execute the model.
Primary source ↗Client inference NPUs only; model support and energy efficiency require actual verification.
Google describes matrix-multiply units and systolic arrays within Cloud TPUs, alongside vector and scalar units.
Primary source ↗Generation-specific sizes and performance are not modeled.