{
  "schemaVersion": 1,
  "topic": "GPU vs NPU vs TPU vs CPU",
  "checked_at": "2026-09-07",
  "claims": [
    {
      "id": "C1",
      "title": "CPU control and GPU parallel work",
      "claim": "NVIDIA describes CPU latency-oriented control and GPU parallel throughput as different design priorities.",
      "url": "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/introduction.html",
      "checked_at": "2026-09-07",
      "type": "primary-documentation",
      "classification": "architecture-specific",
      "boundary": "Qualitative architecture distinction; no universal speed ratio."
    },
    {
      "id": "C2",
      "title": "Data movement is part of the path",
      "claim": "CUDA\u2019s heterogeneous model uses CPU host code to launch GPU work and coordinate data, with memory arrangements varying by system.",
      "url": "https://docs.nvidia.com/cuda/cuda-programming-guide/01-introduction/programming-model.html",
      "checked_at": "2026-09-07",
      "type": "primary-documentation",
      "classification": "architecture-specific",
      "boundary": "Integrated and discrete memory systems differ."
    },
    {
      "id": "C3",
      "title": "NPU execution depends on support",
      "claim": "Microsoft documents execution providers, model-format requirements, and fallback when preferred hardware cannot execute the model.",
      "url": "https://learn.microsoft.com/en-us/windows/ai/npu-devices/",
      "checked_at": "2026-09-07",
      "type": "primary-documentation",
      "classification": "architecture-specific",
      "boundary": "Client inference NPUs only; model support and energy efficiency require actual verification."
    },
    {
      "id": "C4",
      "title": "Cloud TPU specializes in tensor work",
      "claim": "Google describes matrix-multiply units and systolic arrays within Cloud TPUs, alongside vector and scalar units.",
      "url": "https://docs.cloud.google.com/tpu/docs/system-architecture-tpu-vm",
      "checked_at": "2026-09-07",
      "type": "primary-documentation",
      "classification": "architecture-specific",
      "boundary": "Generation-specific sizes and performance are not modeled."
    }
  ],
  "assumptions": [
    "CPU software path assumed available; specialized software flags are entered by the user, not detected.",
    "All memory capacities and working-set estimates are hypothetical teaching values.",
    "This client-NPU path is scoped to inference; the Cloud TPU path requires cloud allowed.",
    "Mixed/custom operations add compiler and fallback cautions rather than asserting hardware impossibility.",
    "Battery priority changes what to measure; it never predicts watts or battery hours."
  ],
  "evidenceClasses": {
    "measuredFacts": "No hardware, model-quality, or corpus measurements are claimed.",
    "derivedResults": "Deterministic arithmetic or editorial rule evaluation; see formulas in README.md.",
    "editorialAssumptions": "Dated synthetic examples, stated scope, and storage policies.",
    "primaryFacts": "Each sourced claim carries its own classification and boundary."
  }
}